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ltc2298/ltc2297/ltc2296 1 229876fa features descriptio u applicatio s u typical applicatio u integrated dual 14-bit adcs sample rate: 65msps/40msps/25msps single 3v supply (2.7v to 3.4v) low power: 400mw/235mw/150mw 74.3db snr 90db sfdr 110db channel isolation at 100mhz multiplexed or separate data bus flexible input: 1v p-p to 2v p-p range 575mhz full power bandwidth s/h clock duty cycle stabilizer shutdown and nap modes pin compatible family105msps: ltc2282 (12-bit), ltc2284 (14-bit) 80msps: ltc2294 (12-bit), ltc2299 (14-bit) 65msps: ltc2293 (12-bit), ltc2298 (14-bit) 40msps: ltc2292 (12-bit), ltc2297 (14-bit) 25msps: ltc2291 (12-bit), ltc2296 (14-bit) 10msps: ltc2290 (12-bit), ltc2295 (14-bit) 64-pin (9mm 9mm) qfn package dual 14-bit, 65/40/25msps low power 3v adcs the ltc 2298/ltc2297/ltc2296 are 14-bit 65msps/ 40msps/25msps, low power dual 3v a/d converters de-signed for digitizing high frequency, wide dynamic range signals. the ltc2298/ltc2297/ltc2296 are perfect for demanding imaging and communications applications with ac performance that includes 74.3db snr and 90db sfdr for signals at the nyquist frequency. dc specs include 1.2lsb inl (typ), 0.5lsb dnl (typ) and no missing codes over temperature. the transitionnoise is a low 1lsb rms . a single 3v supply allows low power operation. a separateoutput supply allows the outputs to drive 0.5v to 3.6v logic. an optional multiplexer allows both channels to share a digital output bus. a single-ended clk input controls converter operation. an optional clock duty cycle stabilizer allows high perfor- mance at full speed for a wide range of clock duty cycles. ltc2298: snr vs input frequency, ?db, 2v range, 65msps + input s/h analog input a analog input b clk aclk b 14-bit pipelined adc core clock/duty cycle control output drivers ov dd ogndmux d13ad0a ov dd ognd 229876 ta01 d13bd0b + output drivers input s/h 14-bit pipelined adc core clock/duty cycle control input frequency (mhz) 0 snr (dbfs) 200 229876 ta01b 50 100 150 7574 73 72 71 70 wireless and wired broadband communication imaging systems spectral analysis portable instrumentation , ltc and lt are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. downloaded from: http:///
ltc2298/ltc2297/ltc2296 2 229876fa absolute axi u rati gs w ww u package/order i for atio uu w ov dd = v dd (notes 1, 2) supply voltage (v dd ) ................................................. 4v digital output ground voltage (ognd) ....... 0.3v to 1v analog input voltage (note 3) ..... 0.3v to (v dd + 0.3v) digital input voltage .................... 0.3v to (v dd + 0.3v) digital output voltage ................ 0.3v to (ov dd + 0.3v) order part number qfn part* marking ltc2298upltc2297up ltc2296up ltc2298cupltc2298iup ltc2297cup ltc2297iup ltc2296cup ltc2296iup consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 4) ltc2298 ltc2297 ltc2296 parameter conditions min typ max min typ max min typ max units resolution 14 14 14 bits (no missing codes) integral linearity error differential analog input (note 5) ? 1.2 5 5 1.2 5 5 1.2 5 lsb differential differential analog input ? 0.5 1 1 0.5 1 1 0.5 1 lsb linearity error offset error (note 6) ?2 21 2 1 2 21 2 1 2 21 2 m v gain error external reference 2.5 0.5 2.5 2.5 0.5 2.5 2.5 0.5 2.5 %fs offset drift 10 10 10 v/ c full-scale drift internal reference 30 30 30 ppm/ c external reference 5 5 5 ppm/ c gain matching 0.3 0.3 0.3 %fs offset matching 2 2 2m v transition noise sense = 1v 1 1 1 lsb rms co verter characteristics u top view 65 up package 64-lead (9mm 9mm) plastic qfn t jmax = 125 c, ja = 20 c/w exposed pad (pin 65) is gnd and must be soldered to pcb a ina + 1 a ina 2 refha 3refha 4 refla 5refla 6 v dd 7 clka 8 clkb 9 v dd 10 reflb 11reflb 12 refhb 13refhb 14 a inb 15 a inb + 16 48 da7 47 da6 46 da5 45 da4 44 da3 43 da2 42 da1 41 da0 40 ofb 39 db13 38 db12 37 db11 36 db10 35 db9 34 db8 33 db7 64 gnd63 v dd 62 sensea61 vcma 60 mode 59 shdna 58 oea 57 ofa 56 da13 55 da12 54 da11 53 da10 52 da9 51 da8 50 ognd 49 ov dd gnd 17 v dd 18 senseb 19 vcmb 20 mux 21 shdnb 22 oeb 23db0 24 db1 25 db2 26 db3 27 db4 28 db5 29 db6 30 ognd 31 ov dd 32 power dissipation ............................................ 1500mw operating temperature range ltc2298c, ltc2297c, ltc2296c ........... 0 c to 70 c ltc2298i, ltc2297i, ltc2296i ..........40 c to 85 c storage temperature range ..................65 c to 125 c order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbflead free part marking: http://www.linear.com/leadfree/ downloaded from: http:///
ltc2298/ltc2297/ltc2296 3 229876fa symbol parameter conditions min typ max units v in analog input range (a in + ? in ) 2.7v < v dd < 3.4v (note 7) 0.5v to 1v v v in,cm analog input common mode (a in + +a in )/2 differential input (note 7) 1 1.5 1.9 v single ended input (note 7) 0.5 1.5 2 v i in analog input leakage current 0v < a in + , a in < v dd ? 1 a i sense sensea, senseb input leakage 0v < sensea, senseb < 1v ? 3 a i mode mode input leakage current 0v < mode < v dd ? 3 a t ap sample-and-hold acquisition delay time 0 ns t jitter sample-and-hold acquisition delay time jitter 0.2 ps rms cmrr analog input common mode rejection ratio 80 db full power bandwidth figure 8 test circuit 575 mhz the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. a in = ?dbfs. (note 4) ltc2298 ltc2297 ltc2296 symbol parameter conditions min typ max min typ max min typ max units snr signal-to-noise ratio 5mhz input 74.3 74.4 74.5 db 12.5mhz input 72.7 74.2 db 20mhz input 72.4 74.4 db 30mhz input 72.1 74.3 db 70mhz input 74.3 73.9 73.4 db 140mhz input 73.9 73.3 73 db sfdr 5mhz input 90 90 90 db 12.5mhz input 76 90 db 20mhz input 75 90 db 30mhz input 75 90 db 70mhz input 85 85 85 db 140mhz input 80 80 80 db sfdr 5mhz input 90 90 90 db 12.5mhz input 80 90 db 20mhz input 80 90 db 30mhz input 78 90 db 70mhz input 90 90 90 db 140mhz input 90 90 90 db s/(n+d) 5mhz input 74.3 74.4 74.5 db 12.5mhz input 72.2 74.2 db 20mhz input 71.9 74.3 db 30mhz input 71.6 74.2 db 70mhz input 74.1 73.6 73.4 db 140mhz input 71.9 71.9 71.8 db i md f in = nyquist, 90 90 90 db nyquist + 1mhz crosstalk f in = nyquist ?10 ?10 ?10 db a alog i put u u dy a ic accuracy u w the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 4) signal-to-noiseplus distortion ratio intermodulationdistortion spurious freedynamic range 4th harmonic or higher spurious freedynamic range 2nd or 3rd harmonic downloaded from: http:///
ltc2298/ltc2297/ltc2296 4 229876fa digital i puts a d digital outputs u u the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 4) i ter al refere ce characteristics uu u (note 4) parameter conditions min typ max units v cm output voltage i out = 0 1.475 1.500 1.525 v v cm output tempco 25 ppm/ c v cm line regulation 2.7v < v dd < 3.3v 3 mv/v v cm output resistance ?ma < i out < 1ma 4 ? symbol parameter conditions min typ max units logic inputs (clk, oe, shdn, mux) v ih high level input voltage v dd = 3v 2v v il low level input voltage v dd = 3v 0.8 v i in input current v in = 0v to v dd ?0 10 a c in input capacitance (note 7) 3 pf logic outputs ov dd = 3v c oz hi-z output capacitance oe = high (note 7) 3 pf i source output source current v out = 0v 50 ma i sink output sink current v out = 3v 50 ma v oh high level output voltage i o = ?0 a 2.995 v i o = ?00 a 2.7 2.99 v v ol low level output voltage i o = 10 a 0.005 v i o = 1.6ma 0.09 0.4 v ov dd = 2.5v v oh high level output voltage i o = ?00 a 2.49 v v ol low level output voltage i o = 1.6ma 0.09 v ov dd = 1.8v v oh high level output voltage i o = ?00 a 1.79 v v ol low level output voltage i o = 1.6ma 0.09 v downloaded from: http:///
ltc2298/ltc2297/ltc2296 5 229876fa power require e ts w u the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 8) ti i g characteristics u w the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 4) note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolutemaximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to ground with gnd and ognd wired together (unless otherwise noted).note 3: when these pin voltages are taken below gnd or above v dd , they will be clamped by internal diodes. this product can handle input currentsof greater than 100ma below gnd or above v dd without latchup. note 4: v dd = 3v, f sample = 65mhz (ltc2298), 40mhz (ltc2297), or 25mhz (ltc2296), input range = 2v p-p with differential drive, unless otherwise noted. note 5: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve.the deviation is measured from the center of the quantization band. note 6: offset error is the offset voltage measured from 0.5 lsb when the output code flickers between 00 0000 0000 0000 and11 1111 1111 1111. note 7: guaranteed by design, not subject to test. note 8: v dd = 3v, f sample = 65mhz (ltc2298), 40mhz (ltc2297), or 25mhz (ltc2296), input range = 1v p-p with differential drive. the supply current and power dissipation are the sum total for both channels withboth channels active. note 9: recommended operating conditions. ltc2298 ltc2297 ltc2296 symbol parameter conditions min typ max min typ max min typ max units v dd analog supply (note 9) 2.7 3 3.4 2.7 3 3.4 2.7 3 3.4 v voltage ov dd output supply (note 9) 0.5 3 3.6 0.5 3 3.6 0.5 3 3.6 v voltage iv dd supply current both adcs at f s(max) 133 150 78 95 50 60 ma p diss power dissipation both adcs at f s(max) 400 450 235 285 150 180 mw p shdn shutdown power shdn = h, 2 2 2 mw (each channel) oe = h, no clk p nap nap mode power shdn = h, 15 15 15 mw (each channel) oe = l, no clk ltc2298 ltc2297 ltc2296 symbol parameter conditions min typ max min typ max min typ max units f s sampling frequency (note 9) 16 5 14 0 12 5 m h z t l clk low time duty cycle stabilizer off 7.3 7.7 500 11.8 12.5 500 18.9 20 500 ns duty cycle stabilizer on 5 7.7 500 5 12.5 500 5 20 500 ns (note 7) t h clk high time duty cycle stabilizer off 7.3 7.7 500 11.8 12.5 500 18.9 20 500 ns duty cycle stabilizer on 5 7.7 500 5 12.5 500 5 20 500 ns (note 7) t ap sample-and-hold 0 0 0 ns aperture delay t d clk to data delay c l = 5pf (note 7) 1.4 2.7 5.4 1.4 2.7 5.4 1.4 2.7 5.4 ns t md mux to data delay c l = 5pf (note 7) 1.4 2.7 5.4 1.4 2.7 5.4 1.4 2.7 5.4 ns data access time c l = 5pf (note 7) 4.3 10 4.3 10 4.3 10 ns after oe bus relinquish time (note 7) 3.3 8.5 3.3 8.5 3.3 8.5 ns pipeline 5 5 5 cycles latency downloaded from: http:///
ltc2298/ltc2297/ltc2296 6 229876fa typical perfor a ce characteristics uw ltc2298: typical inl,2v range, 65msps ltc2298: typical dnl,2v range, 65msps ltc2298: 8192 point fft,f in = 5mhz, ?db, 2v range, 65msps ltc2298: 8192 point fft,f in = 30mhz, ?db, 2v range, 65msps ltc2298: 8192 point fft,f in = 70mhz, ?db, 2v range, 65msps ltc2298: 8192 point fft,f in = 140mhz, ?db, 2v range, 65msps ltc2298: grounded inputhistogram, 65msps ltc2298/ltc2297/ltc2296:crosstalk vs input frequency input frequency (mhz) 0 ?30 crosstalk (db) ?25 ?20 ?15 ?10 ?05 ?00 20 40 60 80 229876 g01 100 code 0 inl error (lsb) 12288 2298 g01 4096 8192 16384 2.01.5 1.0 0.5 0 0.5 1.0 1.5 2.0 code 0 dnl error (lsb) 12288 2298 g02 4096 8192 16384 1.000.75 0.50 0.25 0 0.25 0.50 0.75 1.00 frequency (mhz) 0 amplitude (db) 2298 g03 510152025 30 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00?10 ?20 frequency (mhz) 0 amplitude (db) 2298 g04 510152025 30 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00?10 ?20 frequency (mhz) 0 amplitude (db) 2298 g05 510152025 30 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00?10 ?20 frequency (mhz) 0 amplitude (db) 2298 g06 510152025 30 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00?10 ?20 code 8196 8197 8198 8199 8200 8201 8202 8203 121 1596 9042 21824 20412 10224 2116 172 count 2298 g08 2500020000 15000 10000 5000 0 frequency (mhz) 0 amplitude (db) 2298 g06a 510152025 30 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00?10 ?20 ltc2298: 8192 point 2-tone fft,f in = 28.2mhz and 26.8mhz, ?db, 2v range, 65msps downloaded from: http:///
ltc2298/ltc2297/ltc2296 7 229876fa typical perfor a ce characteristics uw ltc2298: snr and sfdr vssample rate, 2v range, f in = 5mhz, ?db ltc2298: snr and sfdr vsclock duty cycle, 65msps ltc2298: snr vs input level,f in = 30mhz, 2v range, 65msps ltc2298: i ovdd vs sample rate, 5mhz sine wave input, ?db,o vdd = 1.8v ltc2298: i vdd vs sample rate, 5mhz sine wave input, ?db ltc2298: sfdr vs input level,f in = 30mhz, 2v range, 65msps ltc2298: sfdr vs input frequency,?db, 2v range, 65msps input frequency (mhz) 0 100 9590 85 80 75 70 65 150 2298 g10 50 100 200 sfdr (dbfs) sample rate (msps) 50 snr and sfdr (dbfs) 110100 9080 70 60 100 2298 g11 60 70 80 90 010 20 30 40 110 clock duty cycle (%) snr and sfdr (dbfs) 2298 g12 100 9590 85 80 75 70 30 40 50 55 35 45 60 65 70 sfdr: dcs on snr: dcs on snr: dcs off sfdr: dcs off input level (dbfs) ?0 50 snr (dbc and dbfs) ?0 20 ?0 ?0 0 2298 g13 8070 60 50 40 30 20 10 0 dbfs dbc input level (dbfs) 60 50 40 20 ?0 ?0 0 2298 g14 sfdr (dbc and dbfs) 120110 100 9080 70 60 50 40 30 20 dbfs dbc 90dbc sfdrreference line sample rate (msps) i vdd (ma) 2298 g15 155145 135 125 115 105 95 0 20 40 50 10 30 60 70 80 2v range 1v range sample rate (msps) i ovdd (ma) 2298 g16 1210 86 4 2 0 0 20 40 50 10 30 60 70 80 ltc2298: snr vs input frequency,?db, 2v range, 65msps input frequency (mhz) 0 snr (dbfs) 200 2298 g09 50 100 150 7574 73 72 71 70 downloaded from: http:///
ltc2298/ltc2297/ltc2296 8 229876fa typical perfor a ce characteristics uw ltc2297: 8192 point fft,f in = 30mhz, ?db, 2v range, 40msps ltc2297: 8192 point fft,f in = 70mhz, ?db, 2v range, 40msps ltc2297: 8192 point fft,f in = 140mhz, ?db, 2v range, 40msps ltc2297: 8192 point 2-tone fft,f in = 21.6mhz and 23.6mhz, ?db, 2v range, 40msps ltc2297: grounded inputhistogram, 40msps ltc2297: snr vs input frequency,?db, 2v range, 40msps ltc2297: typical inl,2v range, 40msps ltc2297: typical dnl,2v range, 40msps ltc2297: 8192 point fft,f in = 5mhz, ?db, 2v range, 40msps code 0 inl error (lsb) 12288 2297 g01 4096 8192 16384 2.01.5 1.0 0.5 0 0.5 1.0 1.5 2.0 code 0 dnl error (lsb) 12288 2297 g02 4096 8192 16384 1.000.75 0.50 0.25 0 0.25 ?.50?.75 ?.00 frequency (mhz) amplitude (db) 2297 g03 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00?10 ?20 0 51 01 52 0 frequency (mhz) 0 amplitude (db) 2297 g04 51 01 52 0 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00?10 ?20 0 51 01 52 0 frequency (mhz) amplitude (db) 2297 g05 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00?10 ?20 0 51 01 52 0 frequency (mhz) amplitude (db) 2297 g06 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00?10 ?20 frequency (mhz) 0 amplitude (db) 2297 g07 5 1 01 52 0 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00?10 ?20 code 8184 8185 8186 818781888189 8190 81918192 546 36 15714 24558 14833 640 4641 30 count 2297 g08 3000025000 20000 15000 10000 5000 0 4520 input frequency (mhz) 0 snr (dbfs) 200 2297 g09 50 100 150 7574 73 72 71 70 downloaded from: http:///
ltc2298/ltc2297/ltc2296 9 229876fa ltc2297: i ovdd vs sample rate, 5mhz sine wave input, ?db,o vdd = 1.8v ltc2297: i vdd vs sample rate, 5mhz sine wave input, ?db typical perfor a ce characteristics uw ltc2297: sfdr vs input level,f in = 5mhz, 2v range, 40msps ltc2296: typical inl,2v range, 25msps ltc2296: typical dnl,2v range, 25msps ltc2296: 8192 point fft,f in = 5mhz, ?db, 2v range, 25msps ltc2297: sfdr vs input frequency,?db, 2v range, 40msps ltc2297: snr and sfdr vssample rate, 2v range, f in = 5mhz, ?db ltc2297: snr vs input level,f in = 5mhz, 2v range, 40msps input frequency (mhz) 0 100 9590 85 80 75 70 65 150 2297 g10 50 100 200 sfdr (dbfs) sample rate (msps) 0 snr and sfdr (dbfs) 110100 9080 70 60 80 2297 g11 40 20 60 snr sfdr input level (dbfs) ?0 50 snr (dbc and dbfs) ?0 20 ?0 ?0 0 2297 g12 8070 60 50 40 30 20 10 0 dbfs dbc input level (dbfs) 60 50 40 20 ?0 ?0 0 2297 g13 snr (dbc and dbfs) 120110 100 9080 70 60 50 40 30 20 dbfs dbc 90dbc sfdrreference line sample rate (msps) 0 i vdd (ma) 40 2297 g14 10 20 30 50 100 9080 70 60 2v range 1v range sample rate (msps) 0 i ovdd (ma) 4 6 40 2297 g15 20 10 20 30 50 8 code 0 inl error (lsb) 12288 2296 g01 4096 8192 16384 2.01.5 1.0 0.5 0 0.5 1.0 1.5 2.0 code 0 dnl error (lsb) 12288 2296 g02 4096 8192 16384 1.000.75 0.50 0.25 0 0.25 ?.50?.75 ?.00 frequency (mhz) 0 amplitude (db) 2296 g03 24681 0 12 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00?10 ?20 downloaded from: http:///
ltc2298/ltc2297/ltc2296 10 229876fa typical perfor a ce characteristics uw ltc2296: 8192 point 2-tone fft,f in = 10.9mhz and 13.8mhz, ?db, 2v range, 25msps ltc2296: grounded inputhistogram, 25msps ltc2296: snr vs input frequency,?db, 2v range, 25msps ltc2296: sfdr vs inputfrequency, ?db, 2v range, 25msps ltc2296: snr and sfdr vssample rate, 2v range, f in = 5mhz, ?db ltc2296: snr vs input level,f in = 5mhz, 2v range, 25msps ltc2296: 8192 point fft,f in = 30mhz, ?db, 2v range, 25msps ltc2296: 8192 point fft,f in = 70mhz, ?db, 2v range, 25msps ltc2296: 8192 point fft,f in = 140mhz, ?db, 2v range, 25msps frequency (mhz) 0 amplitude (db) 2296 g04 24681 0 12 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00?10 ?20 frequency (mhz) 0 amplitude (db) 2296 g05 24681 0 12 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00?10 ?20 frequency (mhz) 0 amplitude (db) 2296 g06 24681 0 12 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00?10 ?20 frequency (mhz) 0 amplitude (db) 2296 g07 24681 0 12 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00?10 ?20 code 8179 8180 8181 8182 8183 8184 8185 8186 3227 278 18803 22016 853 6919 43 count 2296 g08 2500020000 15000 10000 5000 0 13373 input frequency (mhz) 0 snr (dbfs) 200 2296 g09 50 100 150 7574 73 72 71 70 input frequency (mhz) 0 100 9590 85 80 75 70 65 150 2296 g10 50 100 200 sfdr (dbfs) sample rate (msps) 0 snr and sfdr (dbfs) 110100 9080 70 60 2296 g11 10 20 30 40 50 snr sfdr input level (dbfs) snr (dbc and dbfs) 2296 g12 8070 60 50 40 30 20 10 0 ?0 ?0 ?0 ?0 ?0 ?0 0 dbfs dbc downloaded from: http:///
ltc2298/ltc2297/ltc2296 11 229876fa uu u pi fu ctio s a ina + (pin 1): channel a positive differential analog input. a ina (pin 2): channel a negative differential analog input.refha (pins 3, 4): channel a high reference. short together and bypass to pins 5, 6 with a 0.1 f ceramic chip capacitor as close to the pin as possible. also bypass topins 5, 6 with an additional 2.2 f ceramic chip capacitor and to ground with a 1 f ceramic chip capacitor. refla (pins 5, 6): channel a low reference. short together and bypass to pins 3, 4 with a 0.1 f ceramic chip capacitor as close to the pin as possible. also bypass topins 3, 4 with an additional 2.2 f ceramic chip capacitor and to ground with a 1 f ceramic chip capacitor. v dd (pins 7, 10, 18, 63): analog 3v supply. bypass to gnd with 0.1 f ceramic chip capacitors. clka (pin 8): channel a clock input. the input sample starts on the positive edge.clkb (pin 9): channel b clock input. the input sample starts on the positive edge. reflb (pins 11, 12): channel b low reference. short together and bypass to pins 13, 14 with a 0.1 f ceramic chip capacitor as close to the pin as possible. also bypassto pins 13, 14 with an additional 2.2 f ceramic chip ca- pacitor and to ground with a 1 f ceramic chip capacitor. refhb (pins 13, 14): channel b high reference. short together and bypass to pins 11, 12 with a 0.1 f ceramic chip capacitor as close to the pin as possible. also bypassto pins 11, 12 with an additional 2.2 f ceramic chip ca- pacitor and to ground with a 1 f ceramic chip capacitor. a inb (pin 15): channel b negative differential analog input. a inb + (pin 16): channel b positive differential analog input.gnd (pins 17, 64): adc power ground. senseb (pin 19): channel b reference programming pin. connecting senseb to v cmb selects the internal reference and a 0.5v input range. v dd selects the internal reference and a 1v input range. an external reference greater than 0.5v and less than 1v applied to senseb selects an inputrange of v senseb . 1v is the largest valid input range. v cmb (pin 20): channel b 1.5v output and input common mode bias. bypass to ground with 2.2 f ceramic chip capacitor. do not connect to v cma . ltc2296: i ovdd vs sample rate, 5mhz sine wave input, ?db,o vdd = 1.8v ltc2296: i vdd vs sample rate, 5mhz sine wave input, ?db ltc2296: sfdr vs input level,f in = 5mhz, 2v range, 25msps typical perfor a ce characteristics uw input level (dbfs) 60 50 40 20 ?0 ?0 0 2296 g13 sfdr (dbc and dbfs) 120110 100 9080 70 60 50 40 30 20 dbfs dbc 90dbc sfdrreference line sample rate (msps) i vdd (ma) 2296 g14 7060 50 40 30 0 10 20 51 5 25 30 35 2v range 1v range 0 10 20 51 5 25 30 35 sample rate (msps) i ovdd (ma) 2296 g15 64 2 0 downloaded from: http:///
ltc2298/ltc2297/ltc2296 12 229876fa mux (pin 21): digital output multiplexer control. if mux is high, channel a comes out on da0-da13, ofa; channel b comes out on db0-db13, ofb. if mux is low, the output busses are swapped and channel a comes out on db0- db13, ofb; channel b comes out on da0-da13, ofa. to multiplex both channels onto a single output bus, connect mux, clka and clkb together. shdnb (pin 22): channel b shutdown mode selection pin. connecting shdnb to gnd and oeb to gnd resultsin normal operation with the outputs enabled. connecting shdnb to gnd and oeb to v dd results in normal opera- tion with the outputs at high impedance. connectingshdnb to v dd and oeb to gnd results in nap mode with the outputs at high impedance. connecting shdnb to v dd and oeb to v dd results in sleep mode with the outputs at high impedance.oeb (pin 23): channel b output enable pin. refer to shdnb pin function.db0 ?db13 (pins 24 to 30, 33 to 39): channel b digital outputs. db13 is the msb.ognd (pins 31, 50): output driver ground. ov dd (pins 32, 49): positive supply for the output driv- ers. bypass to ground with 0.1 f ceramic chip capacitor. ofb (pin 40): channel b overflow/underflow output. high when an overflow or underflow has occurred.da0 ?da13 (pins 41 to 48, 51 to 56): channel a digital outputs. da13 is the msb.ofa (pin 57): channel a overflow/underflow output. high when an overflow or underflow has occurred.oea (pin 58): channel a output enable pin. refer to shdna pin function. shdna (pin 59): channel a shutdown mode selection pin. connecting shdna to gnd and oea to gnd resultsin normal operation with the outputs enabled. connecting shdna to gnd and oea to v dd results in normal opera- tion with the outputs at high impedance. connectingshdna to v dd and oea to gnd results in nap mode with the outputs at high impedance. connecting shdna to v dd and oea to v dd results in sleep mode with the outputs at high impedance.mode (pin 60): output format and clock duty cycle stabilizer selection pin. note that mode controls bothchannels. connecting mode to gnd selects offset binary output format and turns the clock duty cycle stabilizer off. 1/3 v dd selects offset binary output format and turns the clock duty cycle stabilizer on. 2/3 v dd selects 2? comple- ment output format and turns the clock duty cycle stabi-lizer on. v dd selects 2? complement output format and turns the clock duty cycle stabilizer off.v cma (pin 61): channel a 1.5v output and input common mode bias. bypass to ground with 2.2 f ceramic chip capacitor. do not connect to v cmb . sensea (pin 62): channel a reference programming pin. connecting sensea to v cma selects the internal reference and a 0.5v input range. v dd selects the internal reference and a 1v input range. an external reference greater than 0.5v and less than 1v applied to sensea selects an inputrange of v sensea . 1v is the largest valid input range. gnd (exposed pad) (pin 65): adc power ground. the exposed pad on the bottom of the package needs to besoldered to ground. uu u pi fu ctio s downloaded from: http:///
ltc2298/ltc2297/ltc2296 13 229876fa fu n ctio n al block diagra uu w figure 1. functional block diagram (only one channel is shown) shift register and correction diff ref amp ref buf 2.2 f 1 f1 f 0.1 f internal clock signals refh refl clock/duty cycle control range select 1.5v reference first pipelined adc stage fifth pipelined adc stage sixth pipelined adc stage fourth pipelined adc stage second pipelined adc stage refh refl clk oe mode ognd ov dd 229876 f01 input s/h sense v cm a in a in + 2.2 f third pipelined adc stage output drivers control logic shdn of d13d0 downloaded from: http:///
ltc2298/ltc2297/ltc2296 14 229876fa dual digital output bus timing (only one channel is shown) ti i g diagra s w u w t ap n + 1 n + 2 n + 4 n + 3 n + 5 n analog input t h t d t l n ?4 n ?3 n ?2 n ?1 clk d0-d13, of 229876 td01 n ?5 n multiplexed digital output bus timing t apb b + 1 b + 2 b + 4 b + 3 b analog input b t apa a + 1 a ?5b ?5 b ?5a ?5 a ?4b ?4 b ?4a ?4 a ?3b ?3 b ?3a ?3 a ?2b ?2 b ?2a ?2 a ?1b ?1 a + 2 a + 4 a + 3 a analog input a t h t d t md t l clka = clkb = mux d0a-d13a, ofa 229876 td02 d0b-d13b, ofb downloaded from: http:///
ltc2298/ltc2297/ltc2296 15 229876fa dynamic performancesignal-to-noise plus distortion ratio the signal-to-noise plus distortion ratio [s/(n + d)] is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components at the adc output. the output is band limited to frequencies above dc to below half the sampling frequency. signal-to-noise ratio the signal-to-noise ratio (snr) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components except the first five harmonics and dc. total harmonic distortion total harmonic distortion is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency. thd is expressed as: thd = 20log ( (v2 2 + v3 2 + v4 2 + . . . vn 2 )/v1 ) where v1 is the rms amplitude of the fundamental fre-quency and v2 through vn are the amplitudes of the second through nth harmonics. the thd calculated in this data sheet uses all the harmonics up to the fifth. intermodulation distortion if the adc input signal consists of more than one spectral component, the adc transfer function nonlinearity can produce intermodulation distortion (imd) in addition to thd. imd is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. if two pure sine waves of frequencies fa and fb are applied to the adc input, nonlinearities in the adc transfer func- tion can create distortion products at the sum and differ- ence frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. the 3rd order intermodulation products are 2fa + fb, applicatio s i for atio wu uu 2fb + fa, 2fa ?fb and 2fb ?fa. the intermodulationdistortion is defined as the ratio of the rms value of either input tone to the rms value of the largest 3rd order intermodulation product. spurious free dynamic range (sfdr) spurious free dynamic range is the peak harmonic or spurious noise that is the largest spectral component excluding the input signal and dc. this value is expressed in decibels relative to the rms value of a full scale input signal. input bandwidth the input bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3db for a full scale input signal. aperture delay time the time from when clk reaches midsupply to the instant that the input signal is held by the sample and hold circuit. aperture delay jitter the variation in the aperture delay time from conversion to conversion. this random variation will result in noise when sampling an ac input. the signal to noise ratio due to the jitter alone will be: snr jitter = ?0log (2 ?f in ?t jitter ) crosstalkcrosstalk is the coupling from one channel (being driven by a full-scale signal) onto the other channel (being driven by a ?dbfs signal). converter operation as shown in figure 1, the ltc2298/ltc2297/ltc2296 are dual cmos pipelined multistep converters. the convert- ers have six pipelined adc stages; a sampled analog input will result in a digitized value five cycles later (see the timing diagram section). for optimal ac performance the analog inputs should be driven differentially. for cost downloaded from: http:///
ltc2298/ltc2297/ltc2296 16 229876fa sensitive applications, the analog inputs can be drivensingle-ended with slightly worse harmonic distortion. the clk input is single-ended. the ltc2298/ltc2297/ ltc2296 have two phases of operation, determined by the state of the clk input pin. each pipelined stage shown in figure 1 contains an adc, a reconstruction dac and an interstage residue amplifier. in operation, the adc quantizes the input to the stage and the quantized value is subtracted from the input by the dac to produce a residue. the residue is amplified and output by the residue amplifier. successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and vice versa. when clk is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the ?nput s/h?shown in the block diagram. at the instant that clk transitions from low to high, the sampled input is held. while clk is high, the held input voltage is buffered by the s/h amplifier which drives the first pipelined adc stage. the first stage acquires the output of the s/h during this high phase of clk. when clk goes back low, the first stage produces its residue which is acquired by the second stage. at the same time, the input s/h goes back to acquiring the analog input. when clk goes back high, the second stage produces its residue which is acquired by the third stage. an identical process is repeated for the applicatio s i for atio wu u u third, fourth and fifth stages, resulting in a fifth stageresidue that is sent to the sixth stage adc for final evaluation. each adc stage following the first has additional range to accommodate flash and amplifier offset errors. results from all of the adc stages are digitally synchronized such that the results can be properly combined in the correction logic before being sent to the output buffer. sample/hold operation and input drive sample/hold operation figure 2 shows an equivalent circuit for the ltc2298/ ltc2297/ltc2296 cmos differential sample-and-hold. the analog inputs are connected to the sampling capaci- tors (c sample ) through nmos transistors. the capacitors shown attached to each input (c parasitic ) are the summa- tion of all other capacitance associated with each input.during the sample phase when clk is low, the transistors connect the analog inputs to the sampling capacitors and they charge to and track the differential input voltage. when clk transitions from low to high, the sampled input voltage is held on the sampling capacitors. during the hold phase when clk is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the adc core for processing. as clk transitions from high to low, the inputs are reconnected to the sampling figure 2. equivalent input circuit v dd v dd v dd 15 ? 15 ? c parasitic 1pfc parasitic 1pf c sample 4pf c sample 4pf ltc2298/ltc2297/ltc2296 a in + a in clk 229876 f02 downloaded from: http:///
ltc2298/ltc2297/ltc2296 17 229876fa capacitors to acquire a new sample. since the samplingcapacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. if the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. if the input change is large, such as the change seen with input frequencies near nyquist, then a larger charging glitch will be seen. single-ended input for cost sensitive applications, the analog inputs can be driven single-ended. with a single-ended input the har- monic distortion and inl will degrade, but the snr and dnl will remain unchanged. for a single-ended input, a in + should be driven with the input signal and a in should be connected to 1.5v or v cm . common mode biasfor optimal performance the analog inputs should be driven differentially. each input should swing 0.5v for the 2v range or 0.25v for the 1v range, around a common mode voltage of 1.5v. the v cm output pin may be used to provide the common mode bias level. v cm can be tied directly to the center tap of a transformer to set thedc input level or as a reference level to an op amp differential driver circuit. the v cm pin must be bypassed to ground close to the adc with a 2.2 f or greater capacitor. input drive impedanceas with all high performance, high speed adcs, the dynamic performance of the ltc2298/ltc2297/ltc2296 can be influenced by the input drive circuitry, particularly the second and third harmonics. source impedance and reactance can influence sfdr. at the falling edge of clk, the sample-and-hold circuit will connect the 4pf sampling capacitor to the input pin and start the sampling period. the sampling period ends when clk rises, holding the sampled input on the sampling capacitor. ideally the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2f encode ); however, this is not always possible and the incomplete settling may degrade the sfdr. the sampling applicatio s i for atio wu uu glitch has been designed to be as linear as possible tominimize the effects of incomplete settling. for the best performance, it is recommended to have a source impedance of 100 ? or less for each input. the source impedance should be matched for the differentialinputs. poor matching will result in higher even order harmonics, especially the second. input drive circuits figure 3 shows the ltc2298/ltc2297/ltc2296 being driven by an rf transformer with a center tapped second- ary. the secondary center tap is dc biased with v cm , setting the adc input signal at its optimum dc level.terminating on the transformer secondary is desirable, as this provides a common mode path for charging glitches caused by the sample and hold. figure 3 shows a 1:1 turns ratio transformer. other turns ratios can be used if the source impedance seen by the adc does not exceed 100 ? for each adc input. a disadvantage of using a transformeris the loss of low frequency response. most small rf transformers have poor performance at frequencies be- low 1mhz. figure 3. single-ended to differential conversionusing a transformer 25 ? 25 ? 25 ? 25 ? 0.1 f a in + a in 12pf 2.2 f v cm ltc2298 ltc2297ltc2296 analog input 0.1 ft1 1:1 t1 = ma/com etc1-1t resistors, capacitors are 0402 package size 229876 f03 figure 4 demonstrates the use of a differential amplifier toconvert a single ended input signal into a differential input signal. the advantage of this method is that it provides low frequency input response; however, the limited gain band- width of most op amps will limit the sfdr at high input frequencies. downloaded from: http:///
ltc2298/ltc2297/ltc2296 18 229876fa 25 ? 0.1 f analog input v cm a in + a in 1k 12pf 229876 f05 2.2 f 1k 25 ? 0.1 f ltc2298 ltc2297ltc2296 figure 5 shows a single-ended input circuit. the imped-ance seen by the analog inputs should be matched. this circuit is not recommended if low distortion is required. applicatio s i for atio wu uu figure 6. recommended front end circuit forinput frequencies between 70mhz and 170mhz figure 8. recommended front end circuit forinput frequencies above 300mhz figure 7. recommended front end circuit forinput frequencies between 170mhz and 300mhz 25 ? 25 ? 12 ? 12 ? 0.1 f a in + a in 8pf 2.2 f v cm analog input 0.1 f 0.1 f t1 t1 = ma/com, etc 1-1-13 resistors, capacitors are 0402 package size 229876 f06 ltc2298 ltc2297ltc2296 figure 5. single-ended drive figure 4. differential drive with an amplifier 25 ? 25 ? 12pf 2.2 f v cm 229876 f04 + + cm analog input high speed differential amplifier a in + a in ltc2298 ltc2297ltc2296 the 25 ? resistors and 12pf capacitor on the analog inputs serve two purposes: isolating the drive circuitry from thesample-and-hold charging glitches and limiting the wideband noise at the converter input. for input frequencies above 70mhz, the input circuits of figure 6, 7 and 8 are recommended. the balun trans- former gives better high frequency response than a flux coupled center tapped transformer. the coupling capaci- tors allow the analog inputs to be dc biased at 1.5v. in figure 8, the series inductors are impedance matching elements that maximize the adc bandwidth. 25 ? 25 ? 0.1 f a in + a in 2.2 f v cm analog input 0.1 f 0.1 f t1 t1 = ma/com, etc 1-1-13 resistors, capacitors are 0402 package size 229876 f07 ltc2298 ltc2297ltc2296 25 ? 25 ? 0.1 f a in + a in 2.2 f v cm analog input 0.1 f 0.1 f t1 t1 = ma/com, etc 1-1-13 resistors, capacitors, inductors are 0402 package size 229876 f08 6.8nh 6.8nh ltc2298 ltc2297ltc2296 downloaded from: http:///
ltc2298/ltc2297/ltc2296 19 229876fa applicatio s i for atio wu uu reference operationfigure 9 shows the ltc2298/ltc2297/ltc2296 refer- ence circuitry consisting of a 1.5v bandgap reference, a difference amplifier and switching and control circuit. the internal voltage reference can be configured for two pin selectable input ranges of 2v ( 1v differential) or 1v ( 0.5v differential). tying the sense pin to v dd selects the 2v range; tying the sense pin to v cm selects the 1v range.the 1.5v bandgap reference serves two functions: its output provides a dc bias point for setting the common mode voltage of any external input circuitry; additionally, the reference is used with a difference amplifier to gener- ate the differential reference levels needed by the internal adc circuitry. an external bypass capacitor is required for the 1.5v reference output, v cm . this provides a high frequency low impedance path to ground for internal andexternal circuitry. the difference amplifier generates the high and low refer-ence for the adc. high speed switching circuits are connected to these outputs and they must be externally bypassed. each output has two pins. the multiple output pins are needed to reduce package inductance. bypass capacitors must be connected as shown in figure 9. each adc channel has an independent reference with its own bypass capacitors. the two channels can be used with the same or different input ranges. other voltage ranges between the pin selectable ranges can be programmed with two external resistors as shown in figure 10. an external reference can be used by applying its output directly or through a resistor divider to sense. it is not recommended to drive the sense pin with a logic device. the sense pin should be tied to the appropriate level as close to the converter as possible. if the sense pin is driven externally, it should be bypassed to ground as close to the device as possible with a 1 f ceramic capacitor. for the best channel matching, connect an external referenceto sensea and senseb. figure 10. 1.5v range adc figure 9. equivalent reference circuit v cm refh sense tie to v dd for 2v range; tie to v cm for 1v range; range = 2 ?v sense for 0.5v < v sense < 1v 1.5v refl 2.2 f 2.2 f internal adchigh reference buffer 0.1 f 229876 f09 4 ? diff amp 1 f 1 f internal adclow reference 1.5v bandgap reference 1v 0.5v range detect and control ltc2298/ltc2297/ltc2296 v cm sense 1.5v 0.75v 2.2 f 12k 1 f 12k 229876 f10 ltc2298 ltc2297ltc2296 input rangethe input range can be set based on the application. the 2v input range will provide the best signal-to-noise perfor- mance while maintaining excellent sfdr. the 1v input range will have better sfdr performance, but the snr will degrade by 5.8db. see the typical performance charac- teristics section. driving the clock input the clk inputs can be driven directly with a cmos or ttl level signal. a sinusoidal clock can also be used along with a low jitter squaring circuit before the clk pin (figure 11). downloaded from: http:///
ltc2298/ltc2297/ltc2296 20 229876fa clk 5pf-30pf etc1-1t 0.1 f v cm ferrite bead differential clock input 229876 f13 ltc2298ltc2297 ltc2296 clk 100 ? 0.1 f 4.7 f ferrite bead clean supply if lvds use fin1002 or fin1018. for pecl, use az1000elt21 or similar 229876 f12 ltc2298ltc2297 ltc2296 applicatio s i for atio wu uu the noise performance of the ltc2298/ltc2297/ltc2296can depend on the clock signal quality as much as on the analog input. any noise present on the clock signal will result in additional aperture jitter that will be rms summed with the inherent adc aperture jitter. in applications where jitter is critical, such as when digitiz- ing high input frequencies, use as large an amplitude as possible. also, if the adc is clocked with a sinusoidal signal, filter the clk signal to reduce wideband noise and distortion products generated by the source. it is recommended that clka and clkb are shorted together and driven by the same clock source. if a small time delay is desired between when the two channels sample the analog inputs, clka and clkb can be driven by two different signals. if this delay exceeds 1ns, the performance of the part may degrade. clka and clkb should not be driven by asynchronous signals. figures 12 and 13 show alternatives for converting a differential clock to the single-ended clk input. the use of a transformer provides no incremental contribution to phase noise. the lvds or pecl to cmos translators provide little degradation below 70mhz, but at 140mhz will degrade the snr compared to the transformer solu- tion. the nature of the received signals also has a large bearing on how much snr degradation will be experi- enced. for high crest factor signals such as wcdma or ofdm, where the nominal power level must be at least 6db to 8db below full scale, the use of these translators will have a lesser impact. figure 11. sinusoidal single-ended clk drive clk 50 ? 0.1 f 0.1 f 4.7 f 1k 1k ferrite bead clean supply sinusoidal clock input 229876 f11 nc7svu04 ltc2298 ltc2297ltc2296 the transformer in the example may be terminated withthe appropriate termination for the signaling in use. the use of a transformer with a 1:4 impedance ratio may be desirable in cases where lower voltage differential signals are considered. the center tap may be bypassed to ground through a capacitor close to the adc if the differential signals originate on a different plane. the use of a capacitor at the input may result in peaking, and depending on transmission line length may require a 10 ? to 20 ? ohm series resistor to act as both a low pass filter for high frequency noise that may be induced into theclock line by neighboring digital signals, as well as a damping mechanism for reflections. figure 13. lvds or pecl clk drive using a transformer figure 12. clk drive using an lvds or pecl to cmos converter downloaded from: http:///
ltc2298/ltc2297/ltc2296 21 229876fa maximum and minimum conversion ratesthe maximum conversion rate for the ltc2298/ltc2297/ ltc2296 is 65msps (ltc2298), 40msps (ltc2297), and 25msps (ltc2296). for the adc to operate properly, the clk signal should have a 50% ( 5%) duty cycle. each half cycle must have at least 7.3ns (ltc2298), 11.8ns(ltc2297), and 18.9ns (ltc2296) for the adc internal circuitry to have enough settling time for proper operation. an optional clock duty cycle stabilizer circuit can be usedif the input clock has a non 50% duty cycle. this circuit uses the rising edge of the clk pin to sample the analog input. the falling edge of clk is ignored and the internal falling edge is generated by a phase-locked loop. the input clock duty cycle can vary from 40% to 60% and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. if the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require a hundred clock cycles for the pll to lock onto the input clock. to use the clock duty cycle stabilizer, the mode pin should be connected to 1/3v dd or 2/3v dd using external resistors. the mode pin controls both channel a andchannel b?he duty cycle stabilizer is either on of off for both channels. the lower limit of the ltc2298/ltc2297/ltc2296 samplerate is determined by droop of the sample-and-hold cir- cuits. the pipelined architecture of this adc relies on storing analog signals on small valued capacitors. junc- tion leakage will discharge the capacitors. the specified minimum operating frequency for the ltc2298/ltc2297/ ltc2296 is 1msps. digital outputs table 1 shows the relationship between the analog input voltage, the digital data bits, and the overflow bit. digital output buffersfigure 14 shows an equivalent circuit for a single output buffer. each buffer is powered by ov dd and ognd, iso- lated from the adc power and ground. the additionaln-channel transistor in the output driver allows operation down to low voltages. the internal resistor in series with the output makes the output appear as 50 ? to external circuitry and may eliminate the need for external dampingresistors. table 1. output codes vs input voltage a in + ?a in d13 ?d0 d13 ?d0 (2v range) of (offset binary) (2? complement) >+1.000000v 1 11 1111 1111 1111 01 1111 1111 1111 +0.999878v 0 11 1111 1111 1111 01 1111 1111 1111 +0.999756v 0 11 1111 1111 1110 01 1111 1111 1110 +0.000122v 0 10 0000 0000 0001 00 0000 0000 0001 0.000000v 0 10 0000 0000 0000 00 0000 0000 0000 ?.000122v 0 01 1111 1111 1111 11 1111 1111 1111 ?.000244v 0 01 1111 1111 1110 11 1111 1111 1110 ?.999878v 0 00 0000 0000 0001 10 0000 0000 0001 ?.000000v 0 00 0000 0000 0000 10 0000 0000 0000 ltc2298/ltc2297/ltc2296 22 229876fa the output should be buffered with a device such as analvch16373 cmos latch. for full speed operation the capacitive load should be kept under 10pf. lower ov dd voltages will also help reduce interference from the digital outputs.data format using the mode pin, the ltc2298/ltc2297/ltc2296 parallel digital output can be selected for offset binary or 2? complement format. note that mode controls both channel a and channel b. connecting mode to gnd or 1/3v dd selects offset binary output format. connecting mode to 2/3v dd or v dd selects 2? complement output format. an external resistor divider can be used to set the1/3v dd or 2/3v dd logic values. table 2 shows the logic states for the mode pin. applicatio s i for atio wu u u output enablethe outputs may be disabled with the output enable pin, oe. oe high disables all data outputs including of. the data ac- cess and bus relinquish times are too slow to allow the outputs to be enabled and disabled during full speed op- eration. the output hi-z state is intended for use during long periods of inactivity. channels a and b have independent output enable pins (oea, oeb). sleep and nap modes the converter may be placed in shutdown or nap modes to conserve power. connecting shdn to gnd results in normal operation. connecting shdn to v dd and oe to v dd results in sleep mode, which powers down all circuitryincluding the reference and typically dissipates 1mw. when exiting sleep mode it will take milliseconds for the output data to become valid because the reference capacitors have to recharge and stabilize. connecting shdn to v dd and oe to gnd results in nap mode, which typically dissipates30mw. in nap mode, the on-chip reference circuit is kept on, so that recovery from nap mode is faster than that from sleep mode, typically taking 100 clock cycles. in both sleep and nap modes, all digital outputs are disabled and enter the hi-z state. channels a and b have independent shdn pins (shdna, shdnb). channel a is controlled by shdna and oea, and channel b is controlled by shdnb and oeb. the nap, sleep and output enable modes of the two channels are completely independent, so it is possible to have one channel operat- ing while the other channel is in nap or sleep mode. digital output multiplexer the digital outputs of the ltc2298/ltc2297/ltc2296 can be multiplexed onto a single data bus. the mux pin is a digital input that swaps the two data busses. if mux is high, channel a comes out on da0-da13, ofa; channel b comes out on db0-db13, ofb. if mux is low, the output busses are swapped and channel a comes out on db0-db13, ofb; channel b comes out on da0-da13, ofa. to multiplex both channels onto a single output bus, connect mux, clka and clkb together (see the timing diagram for the multiplexed mode). the multiplexed data is available on either data bus?he unused data bus can be disabled with its oe pin. table 2. mode pin function clock duty mode pin output format cycle stabilizer 0 offset binary off 1/3v dd offset binary on 2/3v dd 2? complement on v dd 2? complement off overflow bitwhen of outputs a logic high the converter is either overranged or underranged. output driver power separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. the power supply for the digital output buffers, ov dd , should be tied to the same power supply as for the logic being driven. forexample, if the converter is driving a dsp powered by a 1.8v supply, then ov dd should be tied to that same 1.8v supply. ov dd can be powered with any voltage from 500mv up to 3.6v. ognd can be powered with any voltage from gnd upto 1v and must be less than ov dd . the logic outputs will swing between ognd and ov dd . downloaded from: http:///
ltc2298/ltc2297/ltc2296 23 229876fa applicatio s i for atio wu u u grounding and bypassingthe ltc2298/ltc2297/ltc2296 requires a printed cir- cuit board with a clean, unbroken ground plane. a multilayer board with an internal ground plane is recommended. layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital track alongside an analog signal track or under- neath the adc. high quality ceramic bypass capacitors should be used at the v dd , ov dd , v cm , refh, and refl pins. bypass capaci- tors must be located as close to the pins as possible. ofparticular importance is the 0.1 f capacitor between refh and refl. this capacitor should be placed as closeto the device as possible (1.5mm or less). a size 0402 ceramic capacitor is recommended. the large 2.2 f ca- pacitor between refh and refl can be somewhat furtheraway. the traces connecting the pins and bypass capaci- tors must be kept short and should be made as wide as possible. the ltc2298/ltc2297/ltc2296 differential inputs should run parallel and close to each other. the input traces should be as short as possible to minimize capacitance and to minimize noise pickup. heat transfer most of the heat generated by the ltc2298/ltc2297/ ltc2296 is transferred from the die through the bottom- side exposed pad and package leads onto the printed circuit board. for good electrical and thermal perfor- mance, the exposed pad should be soldered to a large grounded pad on the pc board. it is critical that all ground pins are connected to a ground plane of sufficient area. clock sources for undersampling undersampling raises the bar on the clock source and the higher the input frequency, the greater the sensitivity to clock jitter or phase noise. a clock source that degrades snr of a full-scale signal by 1db at 70mhz will degrade snr by 3db at 140mhz, and 4.5db at 190mhz. in cases where absolute clock frequency accuracy is relatively unimportant and only a single adc is required, a 3v canned oscillator from vendors such as saronix orvectron can be placed close to the adc and simply connected directly to the adc. if there is any distance to the adc, some source termination to reduce ringing that may occur even over a fraction of an inch is advisable. you must not allow the clock to overshoot the supplies or performance will suffer. do not filter the clock signal with a narrow band filter unless you have a sinusoidal clock source, as the rise and fall time artifacts present in typical digital clock signals will be translated into phase noise. the lowest phase noise oscillators have single-ended sinusoidal outputs, and for these devices the use of a filter close to the adc may be beneficial. this filter should be close to the adc to both reduce roundtrip reflection times, as well as reduce the susceptibility of the traces between the filter and the adc. if you are sensitive to close-in phase noise, the power supply for oscillators and any buffers must be very stable, or propagation delay variation with supply will translate into phase noise. even though these clock sources may be regarded as digital devices, do not operate them on a digital supply. if your clock is also used to drive digital devices such as an fpga, you should locate the oscillator, and any clock fan-out devices close to the adc, and give the routing to the adc precedence. the clock signals to the fpga should have series termination at the driver to prevent high frequency noise from the fpga disturbing the substrate of the clock fan-out device. if you use an fpga as a programmable divider, you must re-time the signal using the original oscillator, and the re- timing flip-flop as well as the oscillator should be close to the adc, and powered with a very quiet supply. for cases where there are multiple adcs, or where the clock source originates some distance away, differential clock distribution is advisable. this is advisable both from the perspective of emi, but also to avoid receiving noise from digital sources both radiated, as well as propagated in the waveguides that exist between the layers of multi- layer pcbs. the differential pairs must be close together and distanced from other signals. the differential pair should be guarded on both sides with copper distanced at least 3x the distance between the traces, and grounded with vias no more than 1/4 inch apart. downloaded from: http:///
ltc2298/ltc2297/ltc2296 24 229876fa applicatio s i for atio wu u u c210.1 f c270.1 f v dd v dd v dd v dd v dd v cc v cmb c202.2 f c18 1 f c23 1 f c340.1 f c3112pf c17 0.1 f c14 0.1 f c250.1 f c3018pf r29 51 ? l2 47nh c282.2 f c350.1 f c240.1 f c364.7 f e3v dd 3ve5 pwr gnd v dd v cc v cc 229876 ta02 c10.1 f r1633 ? r3222 ? r11k r21k r31k r101k r1449.9 ? r2024.9 ? r18 24.9 ? r24 24.9 ? r17 opt r2224.9 ? r23 51 ? t2 etc1-1t c29 0.1 f c33 0.1 f j3 clock input u6 nc7svu04 u4 nc7sv86p5x u7 nc7sv86p5x u3nc7svu04 c130.1 f c150.1 f c12 4.7 f 6.3v l1 bead v dd c19 0.1 f c110.1 f c4 0.1 f c2 2.2 f c102.2 f c9 1 f c13 1 f r151k j4 analog input b v cc 12 3 4 5 v cmb c80.1 f c612pf c440.1 f r624.9 ? r5 24.9 ? r9 24.9 ? r4 opt r724.9 ? r8 51 ? t1 etc1-1t c3 0.1 f c7 0.1 f j2 analog input a 12 3 5 4 v cma v cma 12 v dd v dd 34 2/3v dd 56 1/3v dd 78 gnd jp1 mode c16 0.1 f u5 24lc025 2523 27 29 31 33 35 37 3921 19 15 1713 9 7 1 3 5 2 4 11 2624 3028 3432 38 40 3937 35 33 31 29 27 25 23 21 19 17 15 13 11 97 5 3 1 40 3201s-40g1 3836 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 3622 20 16 1814 10 86 12 r1310k r1110k r1210k r30 15 ? r n1d 33 ? r n1c 33 ? r n1b 33 ? r n1a 33 ? r n2d 33 ? r n2c 33 ? r n2b 33 ? r n2a 33 ? r n3d 33 ? r n3c 33 ? r n3b 33 ? r n3a 33 ? r n4d 33 ? r n4c 33 ? r n4b 33 ? c391 f c38 0.01 f v cc v dd byp gnd adj out shdn gnd in 12 3 4 8 u8 lt1763 76 5 gnd r26100k r25105k c37 10 f 6.3v e4 gnd v cc u10 nc7sv86p5x v cc c400.1 f c410.1 f u1 ltc2298 a ina + a ina refha refha refla refla v dd clka clkb v dd reflb reflb refhb refhb a inb a inb + 12 3 4 5 6 7 8 9 1011 12 13 14 15 16 4847 46 45 44 43 42 41 40 39 38 37 36 35 34 33 da7da6 da5 da4 da3 da2 da1 da0 ofb db13db12 db11 db10 db9db8 db7 6463 62 61 60 59 58 57 56 55 54 53 52 51 50 49 gnd v dd sensea vcma mode shdna oea ofa da13da12 da11 da10 da9da8 ognd ov dd gndv dd senseb vcmb mux shdnb oeb db0 db1 db2 db3 db4 db5 db6 ognd ov dd 1718 19 20 21 22 23 24 25 26 27 28 29 30 31 32 e2 ext ref b 12 v dd 34 v cm v dd v cmb 56 ext ref jp3 sense e1 ext ref a 12 v dd 34 v cm v dd 56 ext ref jp2 sense a c50.1 f c26 0.1 f v cc b3 b2b4 b5 b6 b7 oe b1 b0 a3 a1 a0 1817 16 15 14 13 12 11 19 2 20 v cc 74vcx245bqx v cc 34 5 6 7 8 9 1 10 a2a7 t/r gnd a5 a4a6 b3 b2b4 b5 b6 b7 oe b1 b0 a3 a1 a0 1817 16 15 14 13 12 11 19 2 20 v cc 74vcx245bqx v cc 34 5 6 7 8 9 1 10 a2a7 t/r gnd a5 a4a6 a0a1 a2 a3 v cc wp scl sda 12 3 4 87 6 5 r27 tbd r31 tbd c3218pf l3 47nh c428.2pf l4 47nh c438.2pf r28 24 ? downloaded from: http:///
ltc2298/ltc2297/ltc2296 25 229876fa applicatio s i for atio wu u u silkscreen top top side downloaded from: http:///
ltc2298/ltc2297/ltc2296 26 229876fa applicatio s i for atio wu u u inner layer 2 gnd inner layer 3 power bottom side downloaded from: http:///
ltc2298/ltc2297/ltc2296 27 229876fa package descriptio u up package 64-lead plastic qfn (9mm 9mm) (reference ltc dwg # 05-08-1705) 9 .00 0.10 (4 sides) note:1. drawing conforms to jedec package outline mo-220 variation wnjr-5 2. all dimensions are in millimeters 3. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side, if present 4. exposed pad shall be solder plated 5. shaded area is only a reference for pin 1 location on the top and bottom of package 6. drawing not to scale pin 1 top mark(see note 5) 0.40 0.10 6463 12 bottom view?xposed pad 7.15 0.10 (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 ?0.05 (up64) qfn 1003 recommended solder pad pitch and dimensions 0.70 0.05 7.15 0.05 (4 sides) 8.10 0.05 9.50 0.05 0.25 0.05 0.50 bsc package outline pin 1 chamfer information furnished by linear technology corporation is believed to be accurate and reliable.however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. downloaded from: http:///
ltc2298/ltc2297/ltc2296 28 229876fa ? linear technology corporation 2004 rd/lt 0106 rev a printed in usa related parts linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com part number description comments ltc1748 14-bit, 80msps 5v adc 76.3db snr, 90db sfdr, 48-pin tssop package ltc1750 14-bit, 80msps, 5v wideband adc up to 500mhz if undersampling, 90db sfdr lt 1993-2 high speed differential op amp 800mhz bw, 70dbc distortion at 70mhz, 6db gain lt1994 low noise, low distortion fully differential input/output low distortion: ?4dbc at 1mhz amplifier/driver ltc2202 16-bit, 10msps, 3.3v adc, lowest noise 150mw, 81.6db snr, 100db sfdr, 48-pin qfn ltc2208 16-bit, 130msps, 3.3v adc, lvds outputs 1250mw, 78db snr, 100db sfdr, 64-pin qfn ltc2220-1 12-bit, 185msps, 3.3v adc, lvds outputs 910mw, 67.7db snr, 80db sfdr, 64-pin qfn ltc2224 12-bit, 135msps, 3.3v adc, high if sampling 630mw, 67.6db snr, 84db sfdr, 48-pin qfn ltc2255 14-bit, 125msps, 3v adc, lowest power 395mw, 72.5db snr, 88db sfdr, 32-pin qfn ltc2280 10-bit, dual, 105msps, 3v adc, low crosstalk 320mw, 61.6db snr, 85db sfdr, 64-pin qfn ltc2282 12-bit, dual, 105msps, 3v adc, low crosstalk 540mw, 70.1db snr, 88db sfdr, 64-pin qfn ltc2284 14-bit, dual, 105msps, 3v adc, low crosstalk 540mw, 72.4db snr, 88db sfdr, 64-pin qfn ltc2286 10-bit, dual, 25msps, 3v adc, low crosstalk 150mw, 61.8db snr, 85db sfdr, 64-pin qfn ltc2287 10-bit, dual, 40msps, 3v adc, low crosstalk 235mw, 61.8db snr, 85db sfdr, 64-pin qfn ltc2288 10-bit, dual, 65msps, 3v adc, low crosstalk 400mw, 61.8db snr, 85db sfdr, 64-pin qfn ltc2289 10-bit, dual, 80msps, 3v adc, low crosstalk 422mw, 61.6db snr, 85db sfdr, 64-pin qfn ltc2290 12-bit, dual, 10msps, 3v adc, low crosstalk 120mw, 71.3db snr, 90db sfdr, 64-pin qfn ltc2291 12-bit, dual, 25msps, 3v adc, low crosstalk 150mw, 71.4db snr, 90db sfdr, 64-pin qfn ltc2292 12-bit, dual, 40msps, 3v adc, low crosstalk 235mw, 71.4db snr, 90db sfdr, 64-pin qfn ltc2293 12-bit, dual, 65msps, 3v adc, low crosstalk 400mw, 71.3db snr, 90db sfdr, 64-pin qfn ltc2294 12-bit, dual, 80msps, 3v adc, low crosstalk 422mw, 70.6db snr, 90db sfdr, 64-pin qfn ltc2295 14-bit, dual, 10msps, 3v adc, low crosstalk 120mw, 74.4db snr, 90db sfdr, 64-pin qfn ltc2296 14-bit, dual, 25msps, 3v adc, low crosstalk 150mw, 74.5db snr, 90db sfdr, 64-pin qfn ltc2297 14-bit, dual, 40msps, 3v adc, low crosstalk 235mw, 74.4db snr, 90db sfdr, 64-pin qfn ltc2298 14-bit, dual, 65msps, 3v adc, low crosstalk 400mw, 74.3db snr, 90db sfdr, 64-pin qfn ltc2299 14-bit, dual, 80msps, 3v adc, low crosstalk 444mw, 73db snr, 90db sfdr, 64-pin qfn lt5512 dc-3ghz high signal level downconverting mixer dc to 3ghz, 21dbm iip3, integrated lo buffer lt5514 ultralow distortion if amplifier/adc driver with digitally 450mhz to 1db bw, 47db oip3, digital gain control 10.5db to 33db controlled gain in 1.5db/step lt5515 1.5ghz to 2.5ghz direct conversion quadrature demodulator high iip3: 20dbm at 1.9ghz, integrated lo quadrature generator lt5516 800mhz to 1.5ghz direct conversion quadrature demodulator high iip3: 21.5dbm at 900mhz, integrated lo quadrature generator lt5517 40mhz to 900mhz direct conversion quadrature demodulator high iip3: 21dbm at 800mhz, integrated lo quadrature generator lt5522 600mhz to 2.7ghz high linearity downconverting mixer 4.5v to 5.25v supply, 25dbm iip3 at 900mhz. nf = 12.5db, 50 ? single ended rf and lo ports downloaded from: http:///

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